How to Inspect Apple Silicon CPU Core Topology and Cache in macOS Terminal Using sysctl

Apple Silicon processors (M1, M2, M3, M4 and their Pro, Max, and Ultra variants) utilize a heterogeneous ARM architecture that pairs high-performance “Firestorm/Avalanche/Everest” cores with high-efficiency “Icestorm/Blizzard/Sawtooth” cores. When benchmarking multithreaded software, optimizing Grand Central Dispatch (GCD) thread pools, or tuning high-performance computing (HPC) engines, developers need precise insight into CPU topology, cluster groupings, L1/L2 cache line sizes, and ARM instruction extensions. In macOS, the kernel exposes these low-level hardware attributes through the sysctl (System Control) interface.

In this guide, you will learn how to query Performance and Efficiency core counts, inspect CPU cache hierarchies, audit hardware-accelerated cryptographic instructions, and filter hardware parameters in macOS Terminal using sysctl.

Understanding Apple Silicon Performance Levels (perflevel)

Unlike traditional symmetric x86 CPUs where all cores share identical clock speeds and cache configurations, macOS abstracts heterogeneous ARM cores into performance tiers (hw.perflevel):

• Performance Level 0 (hw.perflevel0): Corresponds to the high-performance cores (P-cores). These cores feature wide execution pipelines, large private L1 caches, and huge shared L2 caches designed for compute-intensive foreground workloads.
• Performance Level 1 (hw.perflevel1): Corresponds to the energy-efficient cores (E-cores). These cores operate at lower voltages, consume minimal battery power, and process background system tasks, audio processing, and maintenance threads.

The sysctl utility extracts these hardware metrics directly from the XNU kernel and Mach device tree.

Auditing Core Counts: Performance vs. Efficiency Cores

Open Terminal on your Mac. To determine the overall physical and logical core counts:

sysctl hw.physicalcpu hw.logicalcpu

To inspect the exact division between Performance cores and Efficiency cores, query the performance level hierarchy:

sysctl -a | grep "hw.perflevel"

The output returns detailed core allocation tables. For example, on a 12-core M-series chip:

hw.perflevel0.name: Performance
hw.perflevel0.physicalcpu: 8
hw.perflevel0.logicalcpu: 8
hw.perflevel1.name: Efficiency
hw.perflevel1.physicalcpu: 4
hw.perflevel1.logicalcpu: 4

This immediately confirms that the chip contains 8 dedicated P-cores and 4 dedicated E-cores without hyperthreading (since physical and logical core counts are identical).

Inspecting L1 and L2 CPU Cache Architecture

High-throughput algorithms depend heavily on keeping working memory sets inside fast L1 and L2 caches. You can query cache sizes per cluster using sysctl:

sysctl -a | grep -E "hw.perflevel.*(l1|l2|cache)"

Review the printed cache geometry:

• hw.perflevel0.l1icachesize: L1 Instruction cache size per P-core (typically 192 KB on Apple Silicon).
• hw.perflevel0.l1dcachesize: L1 Data cache size per P-core (typically 128 KB).
• hw.perflevel0.l2cachesize: Total shared L2 cache accessible by the P-core cluster (e.g., 16 MB or 32 MB depending on chip tier).
• hw.perflevel1.l2cachesize: Total shared L2 cache for the E-core cluster (typically 4 MB).

To verify the CPU cache line size (critical for memory alignment and preventing false sharing in multithreaded code):

sysctl hw.cachelinesize

Apple Silicon consistently uses a 128-byte cache line size (double the 64-byte line standard of Intel and AMD x86 processors).

Querying CPU Model, Clock Frequency, and Memory Bandwidth

To view the commercial marketing brand string of your Apple Silicon processor:

sysctl machdep.cpu.brand_string

To inspect memory bus and core frequency references:

sysctl hw.cpufrequency hw.busfrequency hw.tbfrequency

The hw.tbfrequency (Timebase Frequency) reports the reference hardware timer frequency (typically 24 MHz on Apple Silicon), which is essential for calculating microsecond timings using mach_absolute_time().

Auditing Hardware-Accelerated ARM Instruction Features

Apple Silicon implements ARMv8/ARMv9 architectures equipped with hardware cryptographic accelerators, matrix multiplication extensions (Apple AMX), and floating-point units. To check available instruction sets:

sysctl -a | grep "hw.optional"

Inspect key capability flags:

Sysctl Flag	Value	Hardware Capability Description
hw.optional.neon	1	ARM Advanced SIMD (NEON) vector math instructions.
hw.optional.arm.FEAT_AES	1	Hardware-accelerated AES cryptographic block cipher instructions.
hw.optional.arm.FEAT_SHA256	1	Hardware-accelerated SHA-256 cryptographic hashing.
hw.optional.floatingpoint	1	Hardware IEEE 754 floating point arithmetic.

These flags confirm that cryptography libraries (such as OpenSSL or Apple CryptoKit) will leverage dedicated hardware execution units rather than slower software routines.

Programmatic Sysctl Extraction in Scripts

To extract values cleanly in automated deployment scripts or build pipelines without trailing labels, use the -n (name only) switch:

# Extract performance core count cleanly
P_CORES=$(sysctl -n hw.perflevel0.logicalcpu)
echo "Performance Cores: $P_CORES"

# Extract total physical memory in bytes
RAM_BYTES=$(sysctl -n hw.memsize)
echo "Physical RAM: $((RAM_BYTES / 1024 / 1024 / 1024)) GB"

This allows scripts to dynamically scale compile jobs (make -j$P_CORES) targeting only high-performance cores, keeping efficiency cores free for interactive system responsiveness.